System and method for individually programmed automatic test grading and scoring

ABSTRACT

Test cards include a group of answer indication areas corresponding to the multiple choice answers for each of a plurality of problems for receiving indicia indicating answer responses to the problems. Correct answer information coded on the card identifies predetermined answer indication areas as corresponding to the correct answers for each problem. Sensing of the correct answer code from each test card automatically programs the apparatus with the correct answer for the problems for comparison with the sensed answer response indicia for grading and scoring the answer responses to the plurality of problems of each test card. A visible correct answer code of plural bit positions includes a number of code bit permutations for identification of each of the answer indication areas as a correct answer to prevent deciphering of the correct answer code. Automatic system control and recording of grading and scoring results is provided.

llriit ttes ll allent Azure, ,l r,

[54] SYSTEM AND MlE'lFlHIUlD 11 111118 lNDlWlIDUALLl/ lPllKGlGRfillVilMlElDl AUTUMATHQ TEST GR/SWING AND S CUllMNG [72] Inventor:Leo 1L. Azure, .lr., Richland, Wash.

[73] Assignee: Automate Corporation, Richland, Wash.

[22] Filed: Aug. 18, 11969 [21] Appl. No.: 850,856

[52} US. Cl. .85/48 8, 235/61.6 E

[51] llnt. Cl. "G090 7/00 [58] ll ield all Search ..35/48, 48 A, 48 B, 8R, 9 R,

[56] References Cited UNITED STATES PATENTS 3,050,248 8/1962 Lindquist..35/48 B X 3,122,844 3/1964 Karash et a1... ..35/9 B 3,221,418 12/1965l-loernes ..35/48 B X 3,267,258 8/1966 Bene ..35/48 B X 3,540,13811/1970 lngeneri ..35/48 B Primary Examiner-Wm. H. GriebAttorney-Brufsky and Staas 57 srcr Test cards include a group of answerindication areas cor responding to the multiple choice answers for eachof a plurality of problems for receiving indicia indicating answerresponses to the problems. Correct answer information coded on the cardidentifies predetermined answer indication areas as corresponding to thecorrect answers for each problem. Sensing of the correct answer codefrom each test card automatically programs the apparatus with thecorrect answer for the problems for comparison with the sensed answerresponse indicia for grading and scoring the answer responses to theplurality of problems of each test card. A visible correct answer codeof plural bit positions includes a number of code bit permutations foridentification of each of the answer indication areas as a correctanswer to prevent deciphering of the correct answer code, Automaticsystem control and recording of grading and scoring results is provided.

24 Claims, 5 Drawing Figures TEST N0.

iubcdef SCORE NAME DATE

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sum 1 nr 3 TEST No. SCORE IO 20 NAME & 2 DATE ubcdef X- ,23 B C D E 24lc: c: [:3 :3 I II 2E3 c: 1- c3 ZV--I I (Uf 3c: E3 E3 E3 4E: c3 C: -IIII 5r: c: c: c: -I I 6c: 1:: c3 c3 c:

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50- c: :3 c3 c: -I II -II I I II II STUDENT TEST 1 NAME No. 2 3 4 noSCORE FIG JOHN DOE M B A 42' INVENTbR LEO L. AZURE, JR.

BY a 12 41:

ATTORNEYS FEB 22 1972 3, M3 3 8 sum a nr 3 Wm 293528 w 052 w m AW m WMIOWA w B C D E ABCDE L. M m w 0 w M S a gfi w .vllw xw m WE w WH A \INH%Y [I Q H mm m m m m M Wm I a J A l W l w zw m fi I lk r m w 5 w? 5 M j-W 1 :1 NE W I IL J IL L r m HIM m w 3 $885 A S M /mm 8 MW m mm@ WW mmmm mm mm mm W8 E 88 Wfi n G .D C d 8 f. A B C D F SYSTEM AND METHOD FORINDIVIDUALLY IPROGIIAMMED AUTOMATIG TEST GRADING AND SCORING BACKGROUNDOF THE INVENTION 1. Field of the Invention This invention relates to amethod and system for automatically grading and scoring answer responsesto problems of the multiple choice type, and more particularly, to sucha method and system providing individual and automatic self-programmingof the grading and scoring operations.

2. State of the Prior Art Systems for automatically grading and scoringresponses, or answer choices, to problems of the multiple choice answertype are well known in the prior art. One such prior art system is setforth in U.S. Pat. No. 3,284,929 of Leo L. Azure, Jr., entitled TestGrading Machine and assigned to the assignee of the present invention.

In such prior art grading and scoring systems, there is typicallyprovided a test card, or answer document having a format comprisinggroups of answer indication areas arranged in rows and corresponding tothe multiple choice answer selections for a plurality of problems.Answer indicia are applied to the answer indication areas by the user ofthe test card, such as a student, to indicate answer responses to theproblems. Such test cards, bearing the answer response indicia, areautomatically processed by the test grading and scoring system forgrading and scoring the answer responses represented by the answerindicia for the plurality of problems.

The grading and scoring operation requires that the system first beprogrammed with the correct answers to the problems for which answerresponses are provided on a given set of test cards. In prior artsystems, the correct answer information typically is provided by amaster storage means which is initially programmed with the correctanswers to a given set of problems, such as in a test to which a largenumber of test cards relate, and with which master information theinformation sensed from each of the test cards is compared.

, The master answer storage means may have a format similar to that ofthe test cards, defining columns and rows of answer indication areas inwhich indicia are applied by the instructor, for example, foridentifying the correct answers to the problems. In the system of thereferenced patent, a matrix plugboard arrangement of master answerstorage is provided in the apparatus. Alternatively, a master cardhaving a format similar to the test cards may be employed, to whichcorrect answer indicia are applied, and which is physically insertedinto the grading apparatus. The master answer storage means is thenscanned in synchronized relationship with the scanning of successiveones of the plurality of test cards for grading the answer responses oneach of the successive test cards. In other systems, the master answerstorage means may comprise a memory of electronic or magnetic type, intowhich the correct answers are entered, such as by sensing and transferfrom a master card.

The system of the referenced patent is available for use in individualschools, affording the benefit that the score results for examinationsare available almost immediately following completion of theexamination. Thus, the system serves as both a teaching tool and alearning tool for the examinees. The system of the referenced patent isparticularly desirable in that it does not require constant attendanceby an operator, and provides for automatically and rapidly grading andscoring a large number of test cards.

Systems of the prior art, as described above, however, are primarilyuseful when at least several and preferably a large number of test cardsall relating to the same examination, and thus the same set of problems,are to be scored in a simultaneous scoring sequence as a group. Thisresults from the requirement that the scoring apparatus be initiallymanually programmed, with master answer information for each differenttest.

As is now well recognized, the most effective teaching techniques, andthose most beneficial to the learning process, require that each studentbe permitted to progress at his own rate. The determination of theprogress of each student, however, requires that some form of testing,or inventory taking, be periodically performed to gauge the progress ofeach student, and preferably that it be done on an almost daily basis.In any given class of students, there exists a wide range of differentlevels of progress of the individual students. Effective testing of alarge number of students at different progress levels requires the useof a corresponding number of tests of different levels of ditficulty.The problem is further compounded by the usual requirement thatdifferent tests be provided for different subjects. Schedules of testsdirected to these purposes are presently commercially available.

Grading and scoring of such tests, however, is very time consuming anddifficult, presenting an onerous task for the instructors and being verywasteful of their time. Further, recording the results of the gradingand scoring of each such test is very time consuming and difficult. Testscon'ng machines of the described prior art type do not satisfy therequirements for testing such a range of different progress levels in aclass of students. This results, since the prior art test scoringmachines must be manually reprogrammed for each different test, and thusfor each different student progress level, rendering such prior artapparatus both time consuming to use, and inefficient in operation. Inaddition, prior art systems fail to provide effective and efficientmeans for recording the testing results, particularly where testing atdifferent progress levels is to be performed.

SUMMARY OF THE INVENTION These and other defects and inadequacies ofprior art test grading and scoring systems and methods are overcome bythe apparatus and method of the invention. In accordance with the testgrading and scoring system and method of the invention, a test card forreceiving indicia representing answer responses to problems of themultiple choice type includes a code which predetermines and identifiesthe correct answer for each problem. The code is sensed and decoded bythe scoring and grading apparatus of the system in timed relationship tothe sensing of the answer response indicia to provide automaticself-programming of the grading operation of the apparatus by each testcard.

In a preferred embodiment, each test card includes a group of answerindication areas corresponding to the multiple choice answers for eachof a plurality of problems, to which areas indicia are selectivelyapplied to identify answer responses, or answer choices, to theproblems. The groups of answer indication areas preferably are arrangedin rows corresponding to each of the plurality of problems, with thecorresponding answer indication areas of successive rows aligned invertical columns.

The coding on each test card identifies a given answer indication areaof each group thereof as the correct answer for the correspondingproblem. The terms code and coding are to be understood to include boththe set of rules by which the data, i.e., the correct answerinformation, is converted from one representation to another, and alsothe set of representations defined by the set of rules selected, as thecontext may require. Thus, the code may be provided in any form adaptedfor automatic processing, both as to the sensing of the coderepresentations and the decoding operations. Preferably, the code isprovided, or recorded on each test card in a represen tation adapted foroptical scanning and for example may include visible or invisible codeindicia. Magnetic and other forms of recording of the coderepresentations may also be employed.

In a preferred embodiment, a plural bit position code is employed. Eachtest card includes a group of code bit positions, for receiving code bitindicia, and corresponding to each group of answer indication areas. Thecode bit indicia are provided in each group of code bit positions inaccordance with any of various permutations which, as defined by thecode, identify a particular answer indication area of the respectiveassociated group thereof as the correct answer for the correspondingproblem.

Preferably, corresponding bit positions of the plurality of rows arealigned in vertical columns. Further, the bit indicia may simplycomprise preprinted, visible marks in the appropriate positions, adaptedfor optical sensing. The aligned arrangement of the answer indicationareas and the code bit positions facilitates the time-synchronizedsequential scanning of the corresponding rows of code bit positions androws of answer indication areas which are respectively associated withthe numbered problems.

A code having a relatively small number of bit positions affords arelatively large number of code bit permutations each of which isavailable to identify a corresponding one of the answer indication areasas a correct answer. On any given card, therefore, for all, orsubstantially all problems having a given answer indication area as thecorrect answer response, different code bit permutations may beprovided, rendering detection of the code by the card user virtuallyimpossible. In

addition, different sets of cards having different arrangements of codebit permutations may be provided wherein the different code bitpermutations nevertheless identify the identical answer indication areasfor the same numbered groups of answer indication areas. Such differentsets of cards are useful for different groups of students taking theidentical examination at different times. In any case, each studenttaking an examination is provided with a test card on which to provideanswer choice indications, wherein that test card is suitably coded inadvance of use thereof by the student, to identify the predeterminedcorrect answers to the problems of that examination.

The apparatus of the invention for grading and scoring theself-programming test cards of the type in accordance with the inventioncomprises means for receiving a plurality of test cards and foradvancing the cards therethrough individually, in succession. There isprovided a sensing station having first means for sensing the code bitindicia identifying predetermined correct answers and second means forsensing the answer indicia provided on the test card in timesynchronized, sequential relationship for the plurality of problems oneach card as the card is advanced therethrough. Decoding means respondto the code bit indicia sensing means to identify the correct answerindication area represented by each group of code bit indicia, insuccession. Since each card individually and automatically programs theapparatus with the correct answer information the successive cards needhave no relationship as to the predetermined correct answers for theproblems thereon.

Synchronization control and logic comparison circuits provide forcomparison of the sensed and decoded correct answer code bits and thecorresponding, sensed answer choice indicia for the plurality ofproblems, individually and in succession, to determine whether theanswer responses are correct or incorrect. Upon completion of thegrading operation, printing counters which accumulate, for example, thenumber of right and/or the number of wrong answer responses on each testcard may be actuated automatically to print the total scores thusaccumulated on the test card.

In accordance with one embodiment of the invention, a system control andoutput recording system includes a typewriter suitably interfaced withthe grading and scoring apparatus for providing general system controlof the operation thereof, and for responding to the grading and scoringoperations thereof to automatically record the grading and scoringresults in a permanent compilation for an entire group of cards, such asthose corresponding to a group of students. In such an embodiment, anindividual test card may be inserted into the apparatus and thetypewriter actuated, such as by typing on a keyboard thereof, to enterthe test card users name or other identification on a suitable recordingform in the typewriter. The typewriter may then initiate the processingof the test card through the grading and scoring apparatus and respondto the operations thereof to provide a problem by problem identificationof correct and incorrect answers and the particular answer given foreach incorrect answer, the total number of correct and similar suchinformation.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 shows, in partial portion, atest card in accordance with the invention;

FIG. 2 is a perspective view of the test grading and scoring apparatusand the system control and output recording means of the system of theinvention;

FIG. 3 is a portion of a record sheet prepared by the output recordingmeans of the invention;

FIG. 4 is a block diagram of the system of the invention; and

FIG. 5 is a schematic, partly in block diagram form, of the decodinglogic and related portions of the system of the invention.

DETAILED DESCRIPTION OF THE INVENTION In FIG. 1 is shown aself-programming test card 10 in accordance with the invention. The card10 includes a plurality of rows or groups of answer indication areas,numbered 1 to 50 to correspond to similarly numbered problems, each ofthe rows including a plurality of areas A through E corresponding tomultiple choice answers to correspondingly numbered problems.Preferably, the group of answer indication areas A to E in each row forthe plurality of rows are aligned in vertical columns.

In the embodiment of the test card 10 shown in FIG. 1, the code foridentification of the predetermined one of the answer indication areascorresponding to the correct answer for each of the problems is providedin a six-code bit position format, with the group of six code bitpositions for a given problem aligned in a horizontal row and with thecorresponding bit positions for the plurality of groups aligned invertical columns.

Referring more specifically to the test card 10, the six-bit positioncode is provided in the bracketed region identified by numeral 20wherein the individual bit positions are identified by the letters athrough f. There optionally may be provided a column of timing marks 30,the centerline of each timing mark being aligned with the centerlines ofthe bit positions in corresponding rows. For a purpose to be described,the rows of code bit positions are longitudinally displaced on the card10 with respect to the corresponding rows of answer indication areas forthe problems. For example, row la comprising the first group of code bitpositions and the corresponding row of answer indication areas forproblem 1 are longitudinally offset. Thus, all of the groups, or rows,of code bit positions la, 2a and 50a are offset from the correspondinganswer indication area rows 1, 2 and 50, respectively, by equal amounts.

The code bit indicia are represented in FIG. 1 as darkened areas such as21, 22, etc. In one embodiment, these indicia may be provided byprinting in dark ink on a card 10 of light background for detection byoptical sensing. As explained more fully hereinafter, a six-bit positioncode provides a total of 64 permutations which are available to identifyindividual ones of the five columns of answer indication areas A throughE. Thus, a total of 12 different code bit permutations may be employedto identify any given one of the indication areas A to E, with four codebit permutations unused. The number of code bit positions, of course,may be increased or decreased in accordance with the desired codingcomplexity to avoid deciphering of the code by a student taking theexamination.

Even the relatively small number of six bit positions, however, is morethan ample to avoid deciphering of the code by a student taking theexamination. In addition, the offset relationship of the bit positionrows and the corresponding answer indication area rows enables theprovision of dummy bit position rows x, y, and 2 which thus serve torender the code even more difficult to decipher. Thus, code bit indiciasuch as 23 and 24 in the row x may be applied to the card lltl to createa further impediment to any unauthorized attempt to decipher the code.In the alternative, the code bit indicia may be printed in magnetic inkon a black background area of the card 110 so that they are not visibleto the student. As a further alternative, a magnetic recording tape maybe provided on the card for recording the correct answer code in anobviously invisible manner.

The card 10 may further include a portion, such as in the upper section,for entering a test number, the score, and the students name, the dateof the examination and similar information in accordance withconventional card formats. Typically, all entries except the score willbe made manually by the student using a given card It). The score, orresults of grading the examination, may be printed automatically in thescore area of the card 10 by the apparatus of the invention. Suchprinting techniques are well known in the art, as disclosed in theabove-referenced patent.

In FIG. 2 is shown a perspective view of test grading and scoringapparatus 60 and a system control and output record ing means 70, inaccordance with the invention. The system control and output recordingsystem 70 is represented'by a typewriter, and is described more fullyhereinafter. The apparatus of the invention may be utilized either in anautomatic sequence mode for scoring a plurality of cards or in acontrolled mode for scoring individual cards, in a manner to bedescribed. When used in the automatic mode, a plurality of test cardsIt) are inserted into a hopper till of the apparatus 60 and are held inplace by a suitable weight 62 for enabling successive feeding ofindividual cards into the apparatus for processing in accordance withthe scoring and grading operations. The scored and graded test cards areexhausted through an exhaust slot 63 and received in a receiving hopper654i, as indicated by the group of stacked test cards It) containedtherein.

The typewriter 70 is electrically connected to the apparatus 60 and maycomprise any suitable signal generating keyboard instrument which, bysuitable interface circuits, may commu nicate with the apparatus 60 as asource of control signals or may respond to signals generated by theapparatus 60 for out put recording purposes.

The function of the typewriter 7t) in FIG. 2 may best be understood withreference to F IG. 3 wherein is shown in greater detail a record sheet71 of the type inserted in the typewriter '70 in FIG. 2. In accordancewith the controlled mode of operation of the system of the invention,wherein individual test cards are graded and scored, a student mayinsert a card it) into the hopper 61 and then type his name and, forexample, a test number for identification of the test on the recordsheet 7ll, in the positions provided therefor. The sheet '7l alsoincludes numbered columns 1 through St) corresponding to the problemnumbering on the test card lit) and a score column.

Upon entry of the test number, for example, or by other suitable keyactuation, the typewriter 70 causes the apparatus 60 to proceed with thescoring and grading of the student card entered therein, and now servesas an output recording instrument responsive to the grading operations.For example, the grading of successive problems causes the typewritercarriage to advance in measured, successive steps to print positionsaligned with the correspondingly numbered columns on the sheet 7!. Foreach correctly answered problem, a blank or other indication, such as adot may be provided. Where multiple answer indication areas are marked,a notation such as M, indicated in column 2, may be provided. Bycontrast, where incorrect answers are provided, the identification ofthe incor' rect answer indication area may automatically be entered asrepresented by the notations B and A in the columns 3 and 50 on thesheet 711. Finally, a total score accumulated by the ap paratus 60 and,if desired, printed on the test card llil may also be transmitted to thetypewriter 70 to effect print out of that score in the score column ofthe sheet 7]. Each student taking the test would proceed in this mannerto enter his card for grading and to type his name on the record sheet71, whereby an automatic compilation of the test results, and thus aninventory of the entire group of students is automatically provided.

In the automatic sequence mode of operation, suitable cod ing may beprovided on each card to be sensed by the apparatus b0 and cause anentry of the card identification on the record sheet 7ll, with thescoring results thereupon being entered in the manner described, insequence for each of a plurality of cards placed in the hopper at.

In FIG. 4 is shown a simplified block diagram comprising the basiccomponent subsystems of the test scoring and grading apparatus and thesystem control and output recording means of the system of theinvention, as shown and discussed with reference to FIG. 2. The cardslid are positioned in a hopper 61 for successive engagement andadvancement by a card transport means llllil through the apparatus forthe grading and scoring operations, and exhaust to the receiving hopper64. Any suitable transport means may be provided, and are well known inthe art.

The cards are transported in succession past a sensing station M2 and amarking station 1114-. The sensing station 1112 includes means forindividually sensing the bit positions a through f of the columns 20,for individually sensing the columns A through E of answer indicationareas of the test cards l0, and for sensing the column 30 of timingmarks, as the cards are successively advanced therethrough. Preferably,the sensing is performed sequentially for the successive timing marks,rows of answer indication areas, and rows, or groups, of the bitpositions of the code 20. For a test card 10 of the type shown in FIG.1, having code bit indicia adapted for opti cal sensing, both of thecode and answer indicia sensing means and the timing mark sensing meansof the station 1112 may comprise suitable illumination sources andphotocell sensing devices. Where magnetic or other types of code indiciaor other types of answer indicia or timing marks are employed,corresponding, compatible types of sensing means are provided.

The cards are successively advanced past the sensing and markingstations H2 and llltl by the transport means in the direction of thearrow, with the top edge of the card It) leading, and at a constantrate. The displacement of the stations H2 and 11d facilitates thepositioning of the sensing and marking means and assures that therespective operations thereof do not interfere. The marking station llllil may include, for example, marking devices for error marking the testcard lit) to indicate incorrect answers and to mark the correct answerindication area for each problem answered incorrectly. A system foreffecting such correct answer marking is disclosed in theabove-referenced patent. The error marking may comprise an edge markingtechnique wherein the marking station illi imprints a mark immediatelyadjacent a longitudinal edge of the card It) and aligned with the row ofanswer indication areas corresponding to the incorrectly answeredproblem. An edge mark technique of this type is disclosed in thecopending application entitled Test Grading and Marking Method andApparatus, Ser. No. 621,275 of Hassfurther and Gates, filed Mar. 7,1967, now US. Pat. No. 3,487,560, and assigned to the assignee of thepresent invention. The marking station 114 may also include a scoreprinting means, such as an accumulating printing counter for print ingthe score on the test card prior to exhaust to the exhaust hopper 64.

The sensed code bit indicia output of sensing station 112 is applied toa decoder circuit and the sensed answer indicia output of the station M2is applied to a shift register 1122. The shift register 1122, asdescribed more fully hereinafter, includes a number of stages equal tothe number of rows by which the corresponding answer indication area ofrows and corresponding code bit position rows are displaced or offset,as above discussed.

The information stored in the shift register 122 is advancedtherethrough in a sequential, stepped manner in response to thedetection of successive timing marks. The advancement may beaccomplished in accordance with successive shift pulses generated byshift pulse generator 116 in response to detection of the successivetiming marks of column 30. As discussed more fully hereinafter, theprovision of the column of timing marks 30 is optional, and these marksmay be identical in appearance to the code bit indicia, if desired.Particularly, regardless of the number of bit positions in the codeemployed, only a single code bit permutation exists in which no indiciais applied to at least one bit position. By not employing thatpermutation, at least one bit position indicia is provided in each row.Thus, the bit position indicia may serve a dual function in detectionfor generating shift pulses. Alternatively, the provision of the columnof timing marks 30 provides a further confusing factor for preventingdeciphering of a visible code presented on a test card, while retainingthe use of the bit permutation having no code bit indicia. In a systememploying the code bit indicia for the generation of the shift pulses, alogic OR gate having six inputs corresponding to the six bit positionsmay be included in the shift pulse generator 116 for responding to thesensed code bit indicia and generating the shift pulses.

In either case, the shift pulses cause the answer indicia applied to theshift register 122 to advance through the successive stages thereof at arate corresponding to the successive shift pulses and thus to thesuccessive sensing of rows of answer indication areas. The number ofstages in the shift register 122 and the rate of advancement of theinformation from the input to the output stages thereof is determined inaccordance with the physical displacement of the sensing and markingstations 112 and 114 and the rate of the test cards by the transport110. Due to the synchronized operating relationship of these components,the sensed answer indicia from a given row of answer indication areas ispresented at the output stage of the shift register 122 simultaneouslywith the presentation of that same row of answer indication areas inposition at the marking station 114 for receiving marking thereon inaccordance with the above-described marking operations. In addition, thenumber of stages of shift register 122 is related, as above described,to the offset of the rows of corresponding code bit positions and answerindication areas on the test card 10. Thus, during the shift interval inwhich a signal representing the sensed answer indicia for a givenproblem is presented at the output stage of the shift register 122, thecode bit indicia identifying the correct answer to that same problem issensed by the sensing station 112 and applied to the decoder 120, whichsubstantially instantaneously decodes the code bit permutation thuspresented to produce a correct answer output.

Thus, during each interval in which the answer response to a givenproblem is presented at the output stage of shift register 122 and thusto the input of the logic and comparison circuits 124, the correctanswer for that same problem IS presented at the output of decoder 120and thus to the logic and comparison circuits 124. The circuits 124compare the answer responses and the correct answer to determinecorrespondence therebetween, and particularly to determine whether theindicated answer response is either right or wrong for that problem. Thecircuits 124 may also recognize the existence of multiple answers whichthen may be separately processed as distinguished from wrong answers andright answers, or which may be processed as wrong answers, as desired.

The outputs from logic and comparison circuits 124 are applied to amarking and scoring logic system 126. The system 126 provides an outputto the marking station 114 for marking the test card in a manner asabove described to indicate wrong answers thereon, to indicate thecorrect answer for each problem answered incorrectly, and to provide atotal score printout, as desired.

The system 126 further provides an input to a typewriter input interfacesystem 128. The interface system 128 further has applied thereto theshift pulses from the shift pulse genera tor 116 and the answer responseoutputs from the shift register 122. The output of interface system 128is applied to a typewriter 70' which may comprise an electrically, codedcontrol typewriter such as shown in FIG. 2.

Output control signals from the typewriter input interface system 128effect the controlled print out of the typewriter 70' to produce therecord sheet 71 as shown in FIG. 3. In this operation, each shift pulsecauses the typewriter carriage to advance such that for each print outoperation of the typewriter, the print out is performed on the recordsheet 71 at the appropriate problem column or score column. Since theanswer responses are applied to the interface system 128 from the shiftregister 122, and depending upon the correctness of the answer responsesin accordance with the output of the logic system 126, in turnresponsive to the outputs of the comparison circuit 124, the interfacesystem 128 may cause the typewriter 70' to print out the answer responsegiven where that response is incorrect. Similarly, the logic system 126may control the interface system 128 to provide for print out of aletter, such as M, to represent multiple answer responses and to printout a total score indication in the appropriate column of record sheet71, as described.

As previously noted, the typewriter 70 may also be employed as a systemcontrol input. The output of typewriter 70 is shown applied to atypewriter output interface system 130 which in turn is applied to asystem control 132. The outputs of the system control 132 are merelyillustratively indicated and represent the provision of suitable controlinputs to the above-discussed operating portions of the system. Forexample these outputs may control the actuation of the transport systemand energization of the sensing and information processing portions ofthe grading and scoring apparatus.

A detailed explanation of an output recording system performinggenerally in accordance with the above-described system is provided inUS. application Ser. No. 739,257, entitled Output Recording System, ofLeo L. Azure, Jr., filed June 24, 1968, now U.S. Pat. No. 3,550,290, andassigned to the assignee of the present invention.

In FIG. 5 is shown a schematic of the decoder shown generally in FIG. 4and related components of the system of the invention, particularlyincluding the sensing station 112, the shift register 122, the logic andcomparison circuits 124 and the marking and scoring logic system 126. InFIG. 5, it is assumed that a column of timing marks is provided on thetest card, and is sensed for providing the shift pulses. Themodification of the system of FIG. 5 to respond to the sensed codeindicia for the generation of shift pulses is obvious and therefore notshown or described.

The sensing station 112 includes a single channel-timing mark-sensingstation 140, a plural channel of bit indicia sensing station 150, and aplural channel answer response indicia sensing station 160.Particularly, the station includes a plurality of sensing channels athrough f, respectively corresponding to the columns of bit positions athrough f the code portions 20 of the card 10. The outputs of thechannels a through f are applied to inverters 151 through 156,respectively, for providing, in accordagce with standard logic notation,the set of outputs Ethrough f and the set of outputs a through f. Thestation includes a plurality of channels A through E corresponding tothe answer indication area columns A through E. The various channels ofthe stations 150 and 160 are aligned in a row in spaced positionscorresponding to the spacing of the various, corresponding columns ofbit positions and answer indication areas on the test card 10 forsensing indicia therein as the card is transported past the sensingstation 112, as diagrammatically shown in FIG. 4.

As discussed previously, a six-bit position code provides a total of 64permutations. With five answer indication areas, and thus five multiplechoice answer responses available for each problem, there is therebyprovided a total of 12 code bit permutations for identification of eachanswer indication area. There remain four unused code bit permutationswhich may be employed as the dummy code indicia in the rows x, y, and zshown in FIG. 1 on the test card ill. These dummy permutations aretherefore not interpreted as defining any correct answer. Depending onthe complexity of the code felt necessary to assure avoidance of codedeciphering, any number of permutations from 1 to 12 may be provided foridentification of each answer indication area A through E as a correctanswer. The selection of the number of permutations is in part aneconomic consideration, in that the number of permutations employeddetermines the number of logic circuits required for decoding.

In HO. 5, the decoder 12th includes a plurality of channels llZllAthrough JlZllE which respectively effect decoding of the sensed code bitindicia each in accordance with a predeten mined code bit permutation toproduce outputs identifying the correct answer to a given problem as theanswer indication areas A through E, respectively. Since each of thedecode logic circuits 120A through IlZllE is identical in construction,although performing the decode logic function in accordance with adifferent code bit permutation, only the decode channel 1120A is shownin detail.

The decode logic channel llZlltA includes a plurality of AND gates suchas 2011, 202, Zllfi each having six input terminals respectivelyconnected to selected ones of the outputs of the six code indiciasensing channel a through f of station 150. The necessary connectionsare readily apparent from the labelling of the sensing station outputterminals and that of the AND gates of the decoding channel, and theconnections have therefore been merely diagrammatically indicated bybrackets. The channel 120A includes six AND-gates 2011 through 206providing for a maximum of six code bit permutations for identificationof answer indication area A as the correct answer for a given problem.Of these six AND gates, only the AND-gates 2011, 202, and 206 are shown.Any fewer number or any greater number, to a total of 12 such AND gatesmay be employed, in accordance with the above discussion of possiblecode bit permutations for identification of a given answer indicationarea.

The decoding operation will be apparent with reference to the logicnotation symbols associated with the inputs to the AND gates, such asAND-gate 201. In accordance with conventional logic notation, theabsence or presence of a bar over a symbol identifies opposite statessuch as the existence or nonexistence of a given condition. Thus, arepresents the presence, and thus sensing, of a code bit indicia a, anda represents the absence of a code bit indicia n. Thus, with respect toAND-gate Zllil, a true output All indicating the decoding of the firstof six code permutations corresponding to identification of A as a go rrct answer is produced when the input conditions a and b, c, d, e, and fare true and thus when a code bit indicia in the bit position of columna has been sensed but no bit positions b through f have been sensed in agiven row of the test card ill. Similarly, it will be seen that A2 istrue at the output of ANDgate 292 when code bit indicia are sensed inbit positions a and b and not in positions throughf. Likewise, a trueoutput Ali: is produced by AND-gate 2% when code bit indicia are sensedin bit positions a and f but not in bit positions b through e in a givenrow. The outputs of AND-gates 2011 through 2% are applied tocorresponding NOR-gates 2111 through 216 which satisfy a logic functionfor controlling AND-gate 220, such that the latter responds to a truecondition for any of the outputs Al through A6 to produce a true outputA indicating that the sensed and decoded code bit indicia in a givengroup or row thereof identifies the answer indication area A as thecorrect answer for the problem associated with that code bit positionrow.

Under a normal condition, and prior to sensing of any code bit indicia,or of any permutation of code bit indicia specifically identifying A asa correct answer, each of the AND-gates 201 through 2% receives at leastone false input and thus produces a false output All to A6, correctlycorresponding to the stated condition. Respectively associated NOR-gates21111 through 216 effectively invert the false state of the logicconditions All through Ad to produce a state of the converse logiclltlll conditions AT through 1T6 to the AND-gate 22d. AND-gate 22!)thereby is enabled to produce a true output A which in turn is invertedby the associated NOR-gate 222 to produce a false output A to the logicand comparison circuits lZ-t. By contrast, when any one of the code bitpermutations identifying A as the correct answer is sensed, thecorresponding one of the AND-gates Zlltll to 2% is enabled and theassociated one of the outputs All through A6 thereof is true. Thecorresponding one of the NOR gate outputs All through A6 is therebyfalse. AND-gate 220 is thus disabled prothicing a false output A.NOR-gate I222 inverts the false output A to produce a true output A,thereby identifying the predetermined answer indication area A ascorresponding to a correct answer to the problem associated with the bitposition row then being sensed. In a similar manner, each of the decoderchannels liZllB through E produces a true output 8 through E,respectively, when the row of bit position indicia then being sensedidentifies that answer indication area as corresponding to thepredetermined correct answer for a given, respectively associatedproblem.

The outputs of the channels 1160A through 160E of the answer responsesensing station 160 are applied as inputs to a first stage of therespectively corresponding shift registers 1122A through 122E. Detectionof an answer in any one of the corresponding columns A through E of agiven row of answer indication areas results in setting the first stageof the corresponding shift register. With concurrent reference to thetest card lit) of HQ. 1, and as above discussed, due to the transport ofthe test card through the sensing station llll2 with the top edgeleading, it will be appreciated that a first shift pulse is applied tothe shift registers 122A through 12215 upon detection of the firsttiming mark 30, and thus preceding sensing of the first row of answerindication areas correspond ing to problem 1. The first stage of theshift registers is thus cleared for receiving information. Since thecode of row x is a dummy code, no decoded correct answer is applied bythe decoder 1120 to the comparison circuit 112d, Answer indicia A isthen detected for problem I, setting the first stage of the shiftregister 1122A, the first stages of the remaining shift registersremaining unset, or cleared. Upon detection of the next successivetiming mark, associated with code row y, the detected answer indiciastored in the first stage of the shift register 122A is advanced to thesecond stage thereof and the second stages of the remaining shiftregisters receive only the cleared state of the first stage. The firststages of all registers are thus prepared for setting in accordance withthe detection of answer indicia from the row of areas corresponding toproblem 2. The sequential advancement of detected answer indicia throughthe shift register stages proceeds in this manner in response to thesuccessive detection of answer indicia in the succeeding rows.

It is apparent, for example, following detection of the second row ofanswer indicia, and of the timing mark as sociated with dummy row 2,that the detected answer indicia A for problem 1 is presented at theoutput stage of the shift register 1122A and thus is applied to thecomparison circuit 124 Shortly thereafter, the sensing station sensesthe row In of code bit indicia, and substantially simultaneouslytherewith, the decoder lIZllA decodes the code bit permutationrepresented by the thus sensed indicia and presents the thus identifiedcorrect answer A for problem I to logic and comparison circuits M ll.The circuits I24 then. perform the grad ing function as above describedby comparison of the answer response A for problem 1 with the correctanswer A as identified, or represented, by the code bit permutation toproduce a right answer output to the marking and scoring logic system26. The operation as to presenting wrong or multiple answer outputs, asdescribed previously with regard to FIG. 4i, is apparent. The answerresponse detected for each problem thus is available at the output ofshift register I22 and is applied to the system 1126 for the recordingpurposes as similarly hereinbefore described. The decoding and gradingoperation proceeds in this manner for sequentially grading all answerresponses indicated on the test card by comparison thereof with thecorresponding decoded correct answers.

Each individual test card thus provides for automatic, selfprogrammingof the test grading and scoring apparatus for effecting the grading andscoring operations as to that individual card and for all cards insuccession. Cards having the same or different code bit permutationsthus may be presented in any random sequence for grading and scoring. Asnoted above, different sets of cards having different code bitpermutations for identifying nevertheless the identical sequence or set,of correct answers for the numbered problems may be provided, as well asdifferent sets of cards having different code bit permutations foridentifying a different set of answers to the numbered problems. As alsonoted, an suitable form of recording of the coded correct answerinformation on each test card may be employed, as desired, which isadapted for sensing and decoding by the apparatus of the invention toprovide for the scoring and grading operations.

What is claimed is:

l. A method for testing with problems of the multiple choice type andfor automatically grading and scoring answer responses to the problems,comprising the steps of:

providing on a test card a code comprising a plurality of bit positionsarranged in groups on the card and respectively corresponding to theproblems and identifying predetermined correct answers for the testproblems,

employing the test card for receiving indicia representing the answerchoices selected as the answer responses for the test problems,

sensing the correct answer code and the answer choice indicia providedon each test card,

decoding the correct answer code to identify the predetermined correctanswers for the problems, and

comparing the predetermined correct answers with the correspondinganswer choice indicia for grading the answer responses to the testproblems.

2. A method as recited in claim 1 further comprising:

providing on each test card different code representations foridentifying the same answer indication area of different groups thereofas the correct answer for the corresponding, different problems.

3. A method as recited in claim 1 further comprising the step of:

providing different sets of test cards for different, respectivelyassociated tests,

providing on each of the test cards of a given set a given arrangementof code representations for identifying the same answer choice as thecorrect answer response for the corresponding, different problems.

4. A method as recited in claim 1 further comprising:

providing different sets of test cards for different, respectivelyassociated tests,

providing on each of the test cards of a given set, a given arrangementof code representations for identifying the correct answers to the testproblems, and

providing on each of the test cards of each other set, a differentarrangement of code representations for identifying the correct answersto the problems of that other, associated test.

5. A method as recited in claim 1 further comprising:

providing different sets of test cards, for a given test,

providing on each of the test cards of a given set a first arrangementof code representations for identifying the correct answers for thatgiven test, and

providing on each of the test cards of each other set, a differentarrangement of code representations for identifying the samepredetermined correct answers to the problems of that same, given test.

6. A method as recited in claim 1 further comprising the steps of:

providing on each test card, groups of answer indication areascorresponding to the multiple choice answers for a plurality of testproblems,

employing the test card for receiving in said groups of answerindication areas thereof indicia representing selected answer choices asthe answer response for the corresponding test problems, and

providing on each test card a correct answer code including a pluralityof code representations respectively related to said groups of answerindication areas for identifying the answer indication areasrepresenting the predetermined correct answers for the correspondingproblems.

7. A method as recited in claim 6 wherein the code representation oneach test card comprises a plural bit position code having a number ofcode bit permutations exceeding the number of answer indication areas ina given group thereof, further comprising, providing groups of differentcode bit permutations for identifying the same answer indication area ofdifferent groups thereof as the correct answer for the corresponding,different problems.

8. A method as recited in claim 7 further comprising the steps of:

providing different sets of test cards for different respectivelyassociated tests,

providing on each of the test cards of a answer indication areas insuccession set, a given arrangement of groups of code bit permutationsfor identifying the answer choice indication areas corresponding to thepredetermined correct answers for the given, associated test, and

providing on each of the test cards of each other, different set, adifferent arrangement of groups of code bit permutations for identifyingthe answer choice indication areas corresponding to the predeterminedcorrect answers for that other, associated test.

9. A method as recited in claim 7 further comprising the steps of:

providing different sets of test cards for a given test,

providing on each of the test cards of a given set a given arrangementof groups of code bit permutations for identifying the answer choiceindication areas corresponding to the predetermined correct answers forthat given test, and

providing on each of the test cards of each other, difierent set, adifferent arrangement of groups of code bit permutations for identifyingthose same answer choice indication areas corresponding to thepredetermined correct answers for that same, given test.

10. A method as recited in claim 7 further comprising providing the coderepresentation on each test card as visible code bit indicia in the codebit positions of the groups thereof in accordance with the preselectedcode bit permutations.

11. A system for grading and scoring answers to problems of the multiplechoice type employing a test card for receiving indicia representinganswer responses to the problems and having a code comprising aplurality of bit positions arranged in groups on the card andrespectively corresponding to the problems and identifying thepredetermined correct answers for the problems, comprising:

a sensing station including first means for sensing answer responseindicia on each test card and second means for sensing the correctanswer code on each test card,

means responsive to said second means for decoding the sensed, correctanswer code to identifying the correct answer for each test problem onthe test card, and

comparison means responsive to said first sensing means and to saiddecoding means for comparing the answer responses sensed by said firstmeans from said answer choice indicia with the correct answersidentified by said decoding means for grading the answer responses tothe problems.

12. A system as recited in claim 11 wherein different coderepresentations identify the same answer indication area as thepredetermined correct answer, and wherein:

said decoding means includes a plurality of decoding channels,respectively identifying a given answer choice indication area as acorrect answer, and

each of said channels is responsive to a number of different coderepresentations sensed from a test card for identifying a respectivelyassociated answer choice indication area as a correct answer.

13. A system as recited in claim llll wherein each test card includes aplurality of groups of answer indication areas, corresponding to themultiple choice answers for a plurality of problems, for receivingindicia representing the answer choices to the problems and a correctanswer code comprising a plural bit position code arranged in groups ofbit positions respectively corresponding to the groups of answerindication areas for receiving indicia in the groups of code bitpositions in accordance with the preselected code bit permutationsidentifying the correct answer choices for the corresponding groups ofanswer indication areas, and wherein:

said first sensing means includes a plurality of channels correspondingto the answer indication areas of said groups thereof for sensing answerindicia in the respectively corresponding answer indication areas, insuccession for the plurality of groups of answer indications areas,

said second sensing means includes a plurality of sensing channelsrespectively corresponding to said code bit posi' tions for selectivelysensing indicia in the respectively corresponding bit positions, insuccession for the plurality of groups of code bit positions,

said decoding means includes a plurality of decoding channelsrespectively identifying a given answer choice indication area of eachof said groups thereof as a correct answer, and

said plurality of decoding channels simultaneously receive the sensedcode bit indicia output of said second sensing means for each of thesuccessively sensed groups of code bit positions and respond torespectively associated, preselected code bit permutations representedby said sensed code bit indicia in each of said groups thereof toidentify the respectively associated answer indication area as thecorrect answer.

14. A system as recited in claim l3 wherein the correspond ing groups ofanswer indication areas and code bit positions are displaced on saidtest card and wherein:

said answer indicia sensing means senses the groups of answer indicationareeas in succession for the plurality of groups thereof,

said code bit indicia sensing means senses the groups of code bitpositions in succession for the plurality of groups thereof insynchronism with and a predetermined time interval after the sensing ofthe corresponding groups of answer indications areas,

said answer indicia sensing means includes means for successivelystoring the answer responses from the groups of sensed answer choiceindicia for the predetermined time interval and for presenting theanswer responses to said comparison means following said predeterminedtime interval of storage thereof, and

said decoding means substantially instantaneously decodes the correctanswers upon sensing of the code bit indicia by said code-sensing meansfor simultaneously presenting said answer responses and said correctanswers to said comparison means for grading the answer responses to theproblems, for all problems in succession.

115. A system as recited in claim llll wherein there is furtherprovided:

system control means and output recording means,

said system control means automatically initiating the grading andscoring of answer responses indicated on each test card, and

said output recording means responding to said comparison means forproviding a permanent record of the results of grading each of theanswer responses on each test card, for all test cards in succession.

to. A system as recited in claim 115 wherein:

said system control means includes means for entering on said permanentrecord an identification of each test card prior to the scoring andgrading of that test card, for all test cards in succession.

N. A system as recited in claim lil wherein, for different problems in agiven test having as the predetermined correct answers thereto the sameanswer choices indication areas there are provided on a test card foruse with that test different code representations for identifying thatsame answer choice as the predetermined correct answer for each of thosedifferent problems, and wherein:

said decoding means includes a plurality of decoding channels,respectively identifying a given answer choice indication area as acorrect answer, and

each of said channels is responsive to a number of different preselectedcode bit permutations sensed from a test card for identifying therespectively associated answer choice indication areas as a correctanswer.

MB. A system as recited in claim l7 wherein the code for each correctanswer is provided on each test card in accordance with the applicationof code bit indicia to selected ones of a predetermined number of codebit positions, and wherein:

said code bit indicia sensing means includes a plurality of bit positionsensing means respectively corresponding to each of said code bitpositions for selectively sensing in dicia in the respectivelycorresponding bit position,

each of said decoding channels includes a plurality of decoding logiccircuits for decoding respectively as sociated ones of the preselectedcode bit permutations represented by the sensed code bit positionindicia and corresponding to the answer choice indication areaidentified by that channel, and

each of said decoding logic circuits includes a plurality of inputsrespectively associated with said plurality of code bit position sensingmeans for responding to the sensing of code bit indicia in therespectively corresponding code bit positions for identifying thecorrect answer associated with that channel when the sensed code bitindicia correspond to the preselected code hit permutation associatedwith that logic circuit.

l9. In a system for automatically grading answers to a plurality ofproblems of the multiple choice type wherein answer responses to theproblems are represented by indicia applied to a test card and having asensing station to sense the answer response indicia, means for sensingand decoding a correct answer code for identifying the correct answersfor the problems and comparison means for comparing the answer responsessensed from the answer response indicia with the corresponding correctanswers decoded from the correct answer code for grading the answerresponses to each problem, the improvement comprising:

a test card for receiving answer choice indicia for indicating answerresponses to each of the problems of a test, and said test card furtherhaving a code comprising a plurality of bit positions arranged in groupson the card and respectively corresponding to the problems andidentifying predetermined correct answers for the test problems.

Bil. in a system as recited in claim 19, the improvement in test cardsfurther comprising:

a plurality of groups of answer indications on the test card,

corresponding to the multiple choice answers for each of a plurality ofproblems, for receiving answer indicia identifying the selected answerchoices to the problems, and

a plurality of groups of code bit positions on the test cardrespectively corresponding to the groups of answer indication areas forreceiving code bit indicia in accordance with the different preselectedcode bit permutations for identifying different ones of the answerindication areas of the respectively corresponding groups thereof as thepredetermined correct answers for the corresponding problems.

21. In a system as recited in claim Ztl, the improvement in test cardsfurther comprising:

,7 15 16 groups of code bit indicia on said test card comprising difsetof problems having a first arrangement of code bit perferent preselectedcode bit permutations for identifying mutations thereon for identifyingthe predetermined corthe same answer indication area of the respectivelycorrect answers to the corresponding set of problems, and respondinggroups of answer indication areas as the each other, different set oftest cards having a different arpredetermined correct answer for thecorresponding rangement of code bit permutations thereon foridentifyproblems. ing the predetermined correct answers for the cor- 22.In a system as recited in claim 21, the improvement in p g, different86! P te t ards further comprising; 24. A system as recited in claim 21,the improvement in test different sets of test cards for use withcorresponding, cards further compl'lsmgi ide ti al et f bl d differentsets of test cards for use with an identical set of differentarrangements of code bit permutations on the dif- Emblems,

ferent sets of test cards for identifying the predetermined E f set ofCards havmg {first @Tangement of Q correct answers for thecorresponding, identical sets of Permutatlcms f' for ldemlfymgpredetermined prob|ems correct answers for the given set of problems,and 23 A System as recited in claim 21 the improvement in test eachother, different set of test cards having a different arcards f thcomprising; rangement of code bit permutations thereon foridentifyplural sets of test cards for use with corresponding, plural thePredetem'med correct answers for that Same sets of problems, given setof problems. a given set of test cards for use with a given,corresponding

1. A method for testing with problems of the multiple choice type and for automatically grading and scoring answer responses to the problems, comprising the steps of: providing on a test card a code comprising a plurality of bit positions arranged in groups on the card and respectively corresponding to the problems and identifying predetermined correct answers for the test problems, employing the test card for receiving indicia representing the answer choices selected as the answer responses for the test problems, sensing the correct answer code and the answer choice indicia provided on each test card, decoding the correct answer code to identify the predetermined correct answers for the problems, and comparing the predetermined correct answers with the corresponding answer choice indicia for grading the answer responses to the test problems.
 2. A method as recited in claim 1 further comprising: providing on each test card different code representations for identifying the same answer indication area of different groups thereof as the correct answer for the corresponding, different problems.
 3. A method as recited in claim 1 further comprising the step of: providing different sets of test cards for different, respectively associated tests, providing on each of the test cards of a given set a given arrangement of code representations for identifying the same answer choice as the correct answer response for the corresponding, different problems.
 4. A method as recited in claim 1 further comprising: providing different sets of test cards for different, respectively associated tests, providing on each of the test cards of a given set, a given arrangement of code representations for identifying the correct answers to the test problems, and providing on each of the test cards of each other set, a different arrangement of code representations for identifying the correct answers to the problems of that other, associated test.
 5. A method as recited in claim 1 further comprising: providing different sets of test cards, for a given test, providing on each of the test cards of a given set a first arrangement of code representations for identifying the correct answers for that given test, and providing on each of the test cards of each other set, a different arrangement of code representations for identifying the same predetermined correct answers to the problems of that same, given test.
 6. A method as recited in claim 1 further comprising the steps of: providing on each test card, groups of answer indication areas corresponding to the multiple choice answers for a plurality of test problems, employing the test card for rEceiving in said groups of answer indication areas thereof indicia representing selected answer choices as the answer response for the corresponding test problems, and providing on each test card a correct answer code including a plurality of code representations respectively related to said groups of answer indication areas for identifying the answer indication areas representing the predetermined correct answers for the corresponding problems.
 7. A method as recited in claim 6 wherein the code representation on each test card comprises a plural bit position code having a number of code bit permutations exceeding the number of answer indication areas in a given group thereof, further comprising, providing groups of different code bit permutations for identifying the same answer indication area of different groups thereof as the correct answer for the corresponding, different problems.
 8. A method as recited in claim 7 further comprising the steps of: providing different sets of test cards for different respectively associated tests, providing on each of the test cards of a answer indication areas in succession set, a given arrangement of groups of code bit permutations for identifying the answer choice indication areas corresponding to the predetermined correct answers for the given, associated test, and providing on each of the test cards of each other, different set, a different arrangement of groups of code bit permutations for identifying the answer choice indication areas corresponding to the predetermined correct answers for that other, associated test.
 9. A method as recited in claim 7 further comprising the steps of: providing different sets of test cards for a given test, providing on each of the test cards of a given set a given arrangement of groups of code bit permutations for identifying the answer choice indication areas corresponding to the predetermined correct answers for that given test, and providing on each of the test cards of each other, different set, a different arrangement of groups of code bit permutations for identifying those same answer choice indication areas corresponding to the predetermined correct answers for that same, given test.
 10. A method as recited in claim 7 further comprising providing the code representation on each test card as visible code bit indicia in the code bit positions of the groups thereof in accordance with the preselected code bit permutations.
 11. A system for grading and scoring answers to problems of the multiple choice type employing a test card for receiving indicia representing answer responses to the problems and having a code comprising a plurality of bit positions arranged in groups on the card and respectively corresponding to the problems and identifying the predetermined correct answers for the problems, comprising: a sensing station including first means for sensing answer response indicia on each test card and second means for sensing the correct answer code on each test card, means responsive to said second means for decoding the sensed, correct answer code to identifying the correct answer for each test problem on the test card, and comparison means responsive to said first sensing means and to said decoding means for comparing the answer responses sensed by said first means from said answer choice indicia with the correct answers identified by said decoding means for grading the answer responses to the problems.
 12. A system as recited in claim 11 wherein different code representations identify the same answer indication area as the predetermined correct answer, and wherein: said decoding means includes a plurality of decoding channels, respectively identifying a given answer choice indication area as a correct answer, and each of said channels is responsive to a number of different code representations sensed from a test card for identifying a respectively associated answer choice indication area as a correct answer.
 13. A system as recited in claim 11 wherein each test card includes a plurality of groups of answer indication areas, corresponding to the multiple choice answers for a plurality of problems, for receiving indicia representing the answer choices to the problems and a correct answer code comprising a plural bit position code arranged in groups of bit positions respectively corresponding to the groups of answer indication areas for receiving indicia in the groups of code bit positions in accordance with the preselected code bit permutations identifying the correct answer choices for the corresponding groups of answer indication areas, and wherein: said first sensing means includes a plurality of channels corresponding to the answer indication areas of said groups thereof for sensing answer indicia in the respectively corresponding answer indication areas, in succession for the plurality of groups of answer indications areas, said second sensing means includes a plurality of sensing channels respectively corresponding to said code bit positions for selectively sensing indicia in the respectively corresponding bit positions, in succession for the plurality of groups of code bit positions, said decoding means includes a plurality of decoding channels respectively identifying a given answer choice indication area of each of said groups thereof as a correct answer, and said plurality of decoding channels simultaneously receive the sensed code bit indicia output of said second sensing means for each of the successively sensed groups of code bit positions and respond to respectively associated, preselected code bit permutations represented by said sensed code bit indicia in each of said groups thereof to identify the respectively associated answer indication area as the correct answer.
 14. A system as recited in claim 13 wherein the corresponding groups of answer indication areas and code bit positions are displaced on said test card and wherein: said answer indicia sensing means senses the groups of answer indication areeas in succession for the plurality of groups thereof, said code bit indicia sensing means senses the groups of code bit positions in succession for the plurality of groups thereof in synchronism with and a predetermined time interval after the sensing of the corresponding groups of answer indications areas, said answer indicia sensing means includes means for successively storing the answer responses from the groups of sensed answer choice indicia for the predetermined time interval and for presenting the answer responses to said comparison means following said predetermined time interval of storage thereof, and said decoding means substantially instantaneously decodes the correct answers upon sensing of the code bit indicia by said code-sensing means for simultaneously presenting said answer responses and said correct answers to said comparison means for grading the answer responses to the problems, for all problems in succession.
 15. A system as recited in claim 11 wherein there is further provided: system control means and output recording means, said system control means automatically initiating the grading and scoring of answer responses indicated on each test card, and said output recording means responding to said comparison means for providing a permanent record of the results of grading each of the answer responses on each test card, for all test cards in succession.
 16. A system as recited in claim 15 wherein: said system control means includes means for entering on said permanent record an identification of each test card prior to the scoring and grading of that test card, for all test cards in succession.
 17. A system as recited in claim 11 wherein, for different problems in a given test having as the predetermined correct answers thereto the same answer choices indication areas there are provided on a test card for use with that test different code representations for identifyinG that same answer choice as the predetermined correct answer for each of those different problems, and wherein: said decoding means includes a plurality of decoding channels, respectively identifying a given answer choice indication area as a correct answer, and each of said channels is responsive to a number of different preselected code bit permutations sensed from a test card for identifying the respectively associated answer choice indication areas as a correct answer.
 18. A system as recited in claim 17 wherein the code for each correct answer is provided on each test card in accordance with the application of code bit indicia to selected ones of a predetermined number of code bit positions, and wherein: said code bit indicia sensing means includes a plurality of bit position sensing means respectively corresponding to each of said code bit positions for selectively sensing indicia in the respectively corresponding bit position, each of said decoding channels includes a plurality of decoding logic circuits for decoding respectively associated ones of the preselected code bit permutations represented by the sensed code bit position indicia and corresponding to the answer choice indication area identified by that channel, and each of said decoding logic circuits includes a plurality of inputs respectively associated with said plurality of code bit position sensing means for responding to the sensing of code bit indicia in the respectively corresponding code bit positions for identifying the correct answer associated with that channel when the sensed code bit indicia correspond to the preselected code bit permutation associated with that logic circuit.
 19. In a system for automatically grading answers to a plurality of problems of the multiple choice type wherein answer responses to the problems are represented by indicia applied to a test card and having a sensing station to sense the answer response indicia, means for sensing and decoding a correct answer code for identifying the correct answers for the problems and comparison means for comparing the answer responses sensed from the answer response indicia with the corresponding correct answers decoded from the correct answer code for grading the answer responses to each problem, the improvement comprising: a test card for receiving answer choice indicia for indicating answer responses to each of the problems of a test, and said test card further having a code comprising a plurality of bit positions arranged in groups on the card and respectively corresponding to the problems and identifying predetermined correct answers for the test problems.
 20. In a system as recited in claim 19, the improvement in test cards further comprising: a plurality of groups of answer indications on the test card, corresponding to the multiple choice answers for each of a plurality of problems, for receiving answer indicia identifying the selected answer choices to the problems, and a plurality of groups of code bit positions on the test card respectively corresponding to the groups of answer indication areas for receiving code bit indicia in accordance with the different preselected code bit permutations for identifying different ones of the answer indication areas of the respectively corresponding groups thereof as the predetermined correct answers for the corresponding problems.
 21. In a system as recited in claim 20, the improvement in test cards further comprising: groups of code bit indicia on said test card comprising different preselected code bit permutations for identifying the same answer indication area of the respectively corresponding groups of answer indication areas as the predetermined correct answer for the corresponding problems.
 22. In a system as recited in claim 21, the improvement in test cards further comprising: different sets of test cards for use with corresponding, identical sets of problems, and different arrangements of code bit permutatiOns on the different sets of test cards for identifying the predetermined correct answers for the corresponding, identical sets of problems.
 23. A system as recited in claim 21, the improvement in test cards further comprising: plural sets of test cards for use with corresponding, plural sets of problems, a given set of test cards for use with a given, corresponding set of problems having a first arrangement of code bit permutations thereon for identifying the predetermined correct answers to the corresponding set of problems, and each other, different set of test cards having a different arrangement of code bit permutations thereon for identifying the predetermined correct answers for the corresponding, different set of problems.
 24. A system as recited in claim 21, the improvement in test cards further comprising: different sets of test cards for use with an identical set of problems, a given set of test cards having a first arrangement of code bit permutations thereon for identifying predetermined correct answers for the given set of problems, and each other, different set of test cards having a different arrangement of code bit permutations thereon for identifying the predetermined correct answers for that same, given set of problems. 